UPP (Universal Phone Processor) IC, current version number is v2.2
Ø DSP cache RAM of 4 kBytes, 2 kBytes lockable, speed 130 MHz, 32 bit
Ø organization
Ø DSP dual access RAM (DARAM) for storing and manipulating data, 32kBytes,
Ø speed 130 MHz, 32 bit organization
Ø DSP single access RAM (SARAM) for storing and manipulating SW variables, 48
Ø kBytes, speed 130 MHz, 32 bit organization
Ø ARM port interface including 4KBytes SRAM for MCU/DSP message transfer (API)
Ø 4KByte MCU cache buffer
Ø ROM for MCU boot code, 2 * 2Kbytes
Ø Thumb memory interface to BootROM, PDRAM, MCUCache, ExtBusC and API
Ø (MemIf)
Ø MCU Memory protection unit (MPU), used to protect MCU memory regions.
Ø transferring data between memory and external flash and SRAM (Ext-BusC)
Ø Hardware support for DSP and MCU co–emulation through JTAG
Ø A large RAM for program data, shared between MCU & DSP (PDRAM).
Ø 4 * 0.5Mbit, (16K x 32bits) Banks, DSP and MCU
Ø 5 * 1Mbit, (32K x 32bits) Banks, MCU only
Ø 4 * 64Kbit, (2K x 32bits) Banks, DSP, MCU and CDMA
Ø Interface between Body (custom systems logic) and MCU/DSP. (BodyIf)
Ø Clocking, timing, sleep and interrupts block (CTSI) for providing system
Ø MCU controlled general purpose USART, MBus USART and general
Ø (PUP)
Ø SIM card interface (SIMIf)
Ø GSM coder (Coder) with EDGE Support
Ø GPRS support (GPRSCip)
Ø Interfaces for keyboard, LCD drivers, audio and UEM control (UIF)
Ø Accessory interface for galvanic connection, NMP IR audio, IrDa SIR
Ø red interface up to 115 kbit/s), IrDa FIR (fast infra red interface 1.152MBit/
Ø UART (AccIf)
Ø SW programmable baseband–RF interface block, Rx Decimators,
Ø Interpolators and Sigma–Delta Modulators, Rx FM Discriminator for
Ø Programmable serial interface to RFIC/discrete PLL etc. (SCU)
Ø -2 PLL's for processor clocks
- 144-pin uBGA package (13 x 13 mm, 0.8 pitch)
- DSP functions:
Ø DSP cache RAM of 4 kBytes, 2 kBytes lockable, speed 130 MHz, 32 bit
Ø organization
Ø DSP dual access RAM (DARAM) for storing and manipulating data, 32kBytes,
Ø speed 130 MHz, 32 bit organization
Ø DSP single access RAM (SARAM) for storing and manipulating SW variables, 48
Ø kBytes, speed 130 MHz, 32 bit organization
Ø ARM port interface including 4KBytes SRAM for MCU/DSP message transfer (API)
- MCU functions:
Ø 4KByte MCU cache buffer
Ø ROM for MCU boot code, 2 * 2Kbytes
Ø Thumb memory interface to BootROM, PDRAM, MCUCache, ExtBusC and API
Ø (MemIf)
Ø MCU Memory protection unit (MPU), used to protect MCU memory regions.
- Processor common functions:
Ø transferring data between memory and external flash and SRAM (Ext-BusC)
Ø Hardware support for DSP and MCU co–emulation through JTAG
Ø A large RAM for program data, shared between MCU & DSP (PDRAM).
- RAM blocks, in 32-bit organization:
Ø 4 * 0.5Mbit, (16K x 32bits) Banks, DSP and MCU
Ø 5 * 1Mbit, (32K x 32bits) Banks, MCU only
Ø 4 * 64Kbit, (2K x 32bits) Banks, DSP, MCU and CDMA
Ø Interface between Body (custom systems logic) and MCU/DSP. (BodyIf)
Ø Clocking, timing, sleep and interrupts block (CTSI) for providing system
Ø MCU controlled general purpose USART, MBus USART and general
Ø (PUP)
Ø SIM card interface (SIMIf)
Ø GSM coder (Coder) with EDGE Support
Ø GPRS support (GPRSCip)
Ø Interfaces for keyboard, LCD drivers, audio and UEM control (UIF)
Ø Accessory interface for galvanic connection, NMP IR audio, IrDa SIR
Ø red interface up to 115 kbit/s), IrDa FIR (fast infra red interface 1.152MBit/
Ø UART (AccIf)
Ø SW programmable baseband–RF interface block, Rx Decimators,
Ø Interpolators and Sigma–Delta Modulators, Rx FM Discriminator for
Ø Programmable serial interface to RFIC/discrete PLL etc. (SCU)
- Other functions:
Ø -2 PLL's for processor clocks